Particularly, though not exclusively, the invention relates to a voltage regulator for FLASH memories, and the description to follow will specifically deal with this field of application for convenience of explanation.
As is well known, there are many types of integrated memory circuits which require on-chip voltage regulators for supplying certain system portions. As an example, FLASH memories require voltages of approximately 5V and 10V for programming their memory cells. These voltage values are provided by a voltage regulator.
Memory cell programning is markedly affected by the voltage applied to its drain terminal. In particular, with non-volatile memory cells of the FLASH type, a low value of the drain voltage results in inadequately slow cell programming, whereas an exceedingly high value results in the non-selected cells of an involved column being partly erased (the so-called "soft erasing" phenomenon).
It is generally held that a circuit including the FLASH memory should be provided with a voltage regulator of a particularly sophisticated type which can supply the cells with an appropriate drain voltage for programming.
A first prior approach consisted of a so-called differential regulation, as schematically illustrated in FIG. 1. FIG. 1 shows generally, in schematic form, a differential regulator 1 comprising a differential stage 2 which is controlled by means of a boost voltage Vpump generated by a voltage booster circuit 3. The differential regulator 1 is operative to limit the current presented on an output terminal OUT during the step of programming the memory cells connected thereto, and stabilize a programming voltage Vpd to the cells, based upon a reference voltage VREF which is received on an input terminal IN'.
The differential stage 2 has an inverting input terminal 4 arranged to receive the reference voltage VREF, and a non-inverting input terminal 5 connected to a ground reference GND and to the output terminal OUT' of the regulator through a feedback network 6 which comprises first R1 and second R2 resistive elements and a filter/compensation capacitor Cf.
In particular, the non-inverting input terminal 5 is connected to the ground reference GND via the first resistive element R1, and connected to the output terminal OUT' via the second resistive element R2. Furthermore, the output terminal OUT' itself is connected to the ground reference GND via a filter/compensation capacitor Cf.
The differential stage 2 also has an output terminal 7 which is connected to the output terminal OUT' of the differential regulator 1 and feedback connected to a supply terminal 8 via a connection transistor M1. The supply terminal 8 of the differential stage 2 is further connected to the booster circuit 3 supplying the boost voltage Vpump.
In the conventional differential regulator 1, the programming voltage Vpd is derived from a control voltage V.sub.REF being delivered to the inverting input terminal 4 of the differential stage 2.
Nevertheless, this prior differential regulator 1 has certain drawbacks of which a major one is the use of a PMOS transistor for the connection transistor M1. The PMOS transistor must have a common source configuration, and accordingly, the loop gain of the structure that contains the differential regulator 1 is made to depend on the number of programmed cells, resulting in increased loop gain. Thus, the capacitor Cf must be provided oversized in order to suit the critical case, such that the structure stability can be ensured under all conditions of operation. This disadvantageously increases the silicon area requirements for integrating the whole structure.
In addition, at the programming stage, a large current begins to flow to the terminals of the memory cells to be programmed. Accordingly, the programming voltage Vpd drops sharply, and the differential stage 2 is allowed to depart from its linear dynamic range and lose its clamp to the programming voltage Vpd. The PMOS connection transistor M1 keep conducting but is unable to control the flow of current to the memory cells being programmed, again by reason of its common source configuration.
The output terminal OUT', where the programming voltage Vpd appears, is then re-charged without any control by the feedback that, in a normal situation, the differential stage 2 would introduce. This situation persists until the differential stage 2 is restored to its linear dynamic range. This may result in objectionable peaking of the drain voltage of the cells being programmed.
Thus, the only way to correct this dangerous situation is to use filter/compensation capacitors Cf of a very high capacitance, with the consequence of disadvantageously increasing the integration area requirements, as previously mentioned.
Furthermore, it should be recalled that in operation of a memory circuit, e.g., of the FLASH type, constructed of cell matrices, several loads may happen to be supplied from the same regulator. As a load is disconnected from the regulator, the power stage of the latter theoretically at once depresses the current being delivered in order to keep the voltage constant.
In actual practice, the feedback loop of the regulator would re-establish the normal condition of operation with some delay, partly dependent on non-linear effects ("slew rate" effect) and on linear effects ("finite band" effect).
During this transient period, the output node of the regulator would be at a higher voltage than is appropriate. This situation can make the immediate clamping of other loads to the regulator problematical.
For example, once a FLASH memory cell programming is completed and the cell is disconnected from the regulator output, a voltage peak would develop at the output. Consequently, the connection of another cell must be deferred, because there is a risk of overprogramming the threshold. This must be prevented, especially with analog FLASH memory cells.
A second prior approach to obviating these deficiencies is described in Italian Patent Application No. MI97A002594, filed by this Applicant on Nov. 21, 1997, and integrated herein by reference.
This document discloses a differential type voltage regulator including a connection transistor which has been modified and configured to drive at its output any number of memory cells, without affecting the loop gain of the structure which contains the regulator and the cells to be driven.
In particular, the modified connection transistor removes the dependence of the structure overall loop gain G.sub.LOOP on the current draw by the driven memory cells. In essence, it is a matter of using a transistor in a source-follower configuration, in particular an NMOS transistor formed from a triple well structure. Not even this prior approach can solve the problems of driving different loads, in particular correct the retarded clamping of a new load, because of the persistence of the overvoltage which is brought about by the driving of the load previously clamped to the regulator.
Thus, nowhere in the prior art is a solution able to provide a voltage regulator whereby a number of loads can be driven with no appreciable delay, and the limitations of prior art regulators be overcome.